As integrated circuits get smaller and faster, and as chip designs become increasingly complex, effective probing and debugging of circuits increases in importance. Probes are used for analysis, by way of example, to observe the effects of applying a signal to the external pins of a device, on the device nodes. Probing systems include mechanical probe, electron beam probe, focused ion beam (FIB), and laser beam probes. Additionally, charged particle beam systems such as FIB systems can perform circuit edits including cuts and joins of the power lines (referred to as nets), which are essential to effective characterization, design debug, and modification. These are illustrated in FIG. 1.
Finding the optimal location on a circuit for any of the above-mentioned acts, i.e., probing the device, performing a net cut or a net join, is a critical step in performing the circuit analysis or debug. Much effort has gone into establishing rules and techniques for determining the suitability of locations therefore on the chip. In particular, U.S. Pat. No. 5,675,499 issued Oct. 7, 1997, describes probe-point placement methods and rules for ranking the suitability of net locations for probing and for cutting a probe-point hole. U.S. Pat. No. 5,675,499 is incorporated herein in its entirety.
Prior methods have required that the operator specify an approximate location on the circuit layout, within which the net is broken into polygons which are evaluated and ranked for suitability for probing, e.g. Providing the location on the circuit layout requires that there be an interface between the circuit schematic and the physical layout. This interface is generally manual, i.e., involving communication between circuit designers and layout engineers, which is often a difficult and time-consuming task, since the circuit design and circuit layout are generally performed by completely different personnel in different, possibly remote, groups.
A method for providing an automated interface between circuit schematic and physical layout, which would enable circuit designers, even those unaware of FIB processes and their limitations, to easily and quickly identify locations on a chip corresponding to desired probing or modification, would greatly streamline and simplify probing, analysis, and modification of circuits, e.g. for debug purposes, as well as providing faster turnaround time.
Additionally, there is a need for increased user input in terms of establishing guidelines, preferences, and weighting of rules for evaluating optimal placement of probes, cuts, and joins.